1. Field of the Invention
The present invention relates to either discrete devices or integrated power semiconductor devices including MOS-gated power devices such as, for example, power MOSFETS, IGBTs, MOS-gated thyristors or other MOS-gated power devices. In particular, the invention relates to a MOS-gated power device having a smaller minimum dimension Lp that is a function of a single feature size and that yields an increased density of MOS-gated power devices per unit area.
2. Discussion of the Related Art
MOS technology power devices as known in the related art are composed of a plurality of elementary functional units integrated in a semiconductor chip. Each elementary functional unit is a vertical MOSFET, and all the elementary functional units are connected in parallel. With this arrangement, each elementary vertical MOSFET contributes a fraction of an overall current capacity of the power device.
A MOS technology power device chip typically includes a lightly doped semiconductor layer of a first conductivity type forming a common drain layer for all the elementary vertical MOSFETS. The lightly doped layer is superimposed over a heavily doped semiconductor substrate. Each elementary functional unit includes a body region of a second conductivity type formed in the common drain layer. U.S. Pat. No. 4,593,302 (Lidow et al.) discloses a so called xe2x80x9ccellularxe2x80x9d power device, wherein the body region of the elementary functional units has a polygonal layout, such as for example a square or hexagonal shape. For this reason, the elementary functional units are also called xe2x80x9celementary cellsxe2x80x9d. In addition, MOS technology power devices are also known in the related art wherein the body region of each elementary functional units is an elongated stripe.
For any of the above power MOS devices, a typical vertical structure of the elementary functional units (i.e. a cross-section view) of the MOS technology power device is as shown in FIG. 1. In FIG. 1, the heavily doped semiconductor substrate is indicated by reference numeral 1 and the lightly doped semiconductor layer is indicated by reference numeral 2. The body region 3 of the elementary functional unit includes a central heavily doped portion 4, called a xe2x80x9cdeep body regionxe2x80x9d, and a lateral lightly doped portion 5, having a lower dopant concentration than the heavily doped deep body region, which forms a channel region of the elementary vertical MOSFET. A doping level of the lateral portions 5 of the body region determines a threshold voltage of the power device. Inside the body region 3, a source region 6 of the same conductivity type as the common drain layer 2 is formed. A thin oxide layer 7 (a gate oxide layer) and a polysilicon layer 8 (a gate electrode of the power device) cover a surface of the semiconductor layer 2 between the body regions 3, and the layers also extend over the lightly doped lateral portion of the body regions. The polysilicon layer 8 is covered by a dielectric layer 9 in which contact windows 11 are opened over each body region to allow a superimposed metal layer 10 (a source electrode of the power device) to be deposited through the contact window and to contact the source regions 6 and the deep body region 4.
In the structure of FIG. 1, a short-circuit is defined between the source region and the deep body region to prevent a parasitic bipolar junction transistor having an emitter, a base and a collector respectively formed by the source region 6, the deep body region 4 and the heavily doped semiconductor substrate 1, from triggering on. The parasitic bipolar transistor will trigger xe2x80x9conxe2x80x9d if the lateral current flow in the body below the source produces a voltage drop greater than approximately 0.7V, forward biasing the emitter-to-base (EB) junction. The deep body region 4 increases the ruggedness of the power device because it reduces the base resistance of such a parasitic transistor.
The structure of FIG. 1 is manufactured by forming the common drain layer 2 over the heavily doped substrate 1, generally by means of an epitaxial growth. The thin oxide layer 7 is thermally grown over an active area of the common drain layer 2, wherein the elementary functional units of the MOS technology power device will be formed, and the polysilicon layer 8 is deposited on the thin oxide layer. The deep body regions 4 are formed by selective introduction of a high dose of a dopant to form the central heavily doped deep body regions 4. Windows 12 are formed in the gate oxide layer and the polysilicon layer by a selective etching of the polysilicon and gate oxide layers via a second mask to open the windows 12 where the elementary functional units will be formed. The lateral lightly doped portions of the body regions are then formed by selective introduction of a low dose of dopants into the common drain layer through the windows to form the lightly doped portions of the body regions. Next, the source regions 6 are formed as will be described in more detail below, followed by deposition of the dielectric layer 9 and selective etching thereof to open the contact windows 11. The metal layer 10 is then deposited and patterned.
This process involves the use of a minimum of four photolithographic masks: a first mask is used for the formation of the deep body regions 4; a second mask is used to selectively etch the polysilicon 8 and gate oxide 7 layers; a third mask is used to form the source regions 6 and a fourth mask is used to open the contact windows 11 in the dielectric layer 9. The mask for the introduction of the dopants forming the source regions is provided partially by the polysilicon and oxide layers, and partially by photoresist isles over a middle portion of the deep body regions 4. The photoresist isles are formed by depositing a photoresist layer over the common drain layer, selectively exposing the photoresist layer to a light source, and selectively removing the photoresist layer to provide the photoresist isles. Referring again to FIG. 1, a dimension Lp of each window 12 in the polysilicon 8 and gate oxide 7 layers is given by equation (1 ):
Lp=a+2txe2x80x83xe2x80x83(1)
where xe2x80x9caxe2x80x9d is the width of the contact window 11 in the dielectric layer 9 and xe2x80x9ctxe2x80x9d is the distance between an edge of the polysilicon 8 and gate oxide 7 layers and an edge of the window 11 in the dielectric layer 9. The dimension xe2x80x9caxe2x80x9d of the contact window is given by equation (2):
a=c+2bxe2x80x83xe2x80x83(2)
where xe2x80x9cbxe2x80x9d is a distance between an edge of the contact window 11 and an inner edge of the source region 6, or in other words the length of the source region available to be contacted by the metal layer 10, and xe2x80x9ccxe2x80x9d is the dimension of a surface of the deep body region wherein the source regions are absent or in other words the distance between the inner edges of the source regions, corresponding to the length of the surface of the deep body region available to be contacted by the metal layer. The dimension Lp is therefore given by equation (3):
Lp=c+2b+2txe2x80x83xe2x80x83(3)
Accordingly, the elementary functional units of the related art have the dimension Lp determined by xe2x80x9cthree feature sizesxe2x80x9d, in particular the dimension Lp depends on the parameters xe2x80x9ccxe2x80x9d, xe2x80x9cbxe2x80x9d and xe2x80x9ctxe2x80x9d.
In MOS technology power devices, the electrical parameters to be optimized are the output resistance in the xe2x80x9conxe2x80x9d condition Ron, a gate-to-drain capacitance (feedback capacitance) and a gate-to-source capacitance (input capacitance) of the MOS technology power device for a specific die size and breakdown voltage. The output resistance Ron is the sum of several components, each of which is associated with a particular physical region of the device. More specifically, Ron is made up of the components as shown in equation (4):
Ron=Rc+Racc+Rjfet+Repixe2x80x83xe2x80x83(4)
where Rc is a channel resistance associated with the channel region, Racc is an accumulation region resistance associated with a surface portion of the common drain layer between the body regions, Rjfet is a resistance associated with a portion of the common drain layer between depletion regions of the body regions 5, and Repi is a resistance associated with a portion of the drain layer beneath the body regions.
The channel resistance Rc depends on process parameters such as the dopant concentration of the channel region. In other words Rc is proportional to the threshold voltage of the MOS technology power device, and to the channel length. The accumulation region resistance Racc depends on the distance xe2x80x9cdxe2x80x9d between two adjacent body regions, and decreases as such distance decreases. The Rjfet resistance depends on a resistivity of the common drain layer and on the distance xe2x80x9cdxe2x80x9d between the body regions, and increases as such a distance decreases. The Repi resistance depends on the resistivity and a thickness of the common drain layer, two parameters which also determine a maximum voltage (Bvmax) that can be sustained by the MOS technology power device. Bvmax increases as the resistivity increases, as long as the epi layer is thick enough. The resistivity and the thickness are optimized for the lowest value of Repi. Further, the output resistance Ron is inversely proportional to an overall channel length of the MOS technology power device. In other words Ron is inversely proportional to a sum of the channel of the individual elementary functional units that make up the MOS technology power device. The longer the channel length per unit area of the MOS technology power device, the lower the output resistant Ron per unit area.
Thus, in order to reduce the Ron it is desirable to scale down the dimensions of the elementary functional units and in particular the distance xe2x80x9cdxe2x80x9d between the body regions as long as Rjfet is not significantly increased, or in other words to increase a density of elementary functional units per unit area. A reduction of the distance xe2x80x9cdxe2x80x9d between the body regions has a further advantage of lowering the input and feedback capacitances of the MOS technology power device, thus improving its dynamic performance. Also, in high-voltage MOS technology power devices, reducing the distance xe2x80x9cdxe2x80x9d between the body regions increases the device""s ruggedness under switching conditions. A recent technological trend has therefore been toward increasing the density of elementary functional units per unit area, and MOS technology power devices with a density of up to six million elementary cells per square inch can be fabricated.
The structure of the related art however poses some limitations to the further reduction of the dimensions thereof. These limitations are essentially determined by a resolution and alignment characteristics of the photolithographic apparatus used in the process to manufacture the MOS technology power device. Referring again to FIG. 1, it is known that the dimension xe2x80x9ccxe2x80x9d must be sufficiently large enough to guarantee that the metal layer 10 contacts the body region, and can only be scaled down to the resolution limit of the photolithographic apparatus used to provide the region xe2x80x9ccxe2x80x9d. In addition, the dimension xe2x80x9cbxe2x80x9d must be sufficiently large enough to guarantee that the metal layer contacts the source region 6, and must also allow for any alignment errors between the mask defining the contact window 11 in the dielectric layer 9 and the mask for the formation of the source regions. Further, the dimension xe2x80x9ctxe2x80x9d must be sufficiently large enough to guarantee that the polysilicon layer 8 is electrically insulated from the metal layer and must also take into account any alignment errors between the masks for the definition of the windows 12 in the polysilicon layer and the mask for forming the contact windows in the dielectric layer.
In addition, the structure of the elementary functional units according to the related art does not allow reduction of the distance xe2x80x9cdxe2x80x9d between the elementary functional units below certain values that depend on a voltage rating of the MOS technology power device. For example, the distance xe2x80x9cdxe2x80x9d is approximately 5 xcexcm for low-voltage devices and in a range from 10 xcexcm to 30 xcexcm for medium to high-voltage devices. A reduction of the distance xe2x80x9cdxe2x80x9d below the specified values would in fact cause a rapid increase in the Rjfet component of the Ron of the MOS technology power device, thereby increasing the value of Ron.
In view of the state of the art described, it is an object of the present invention to provide a new MOS technology power device structure which provides an improvement to the MOS technology power devices of the related art.
It is an object of the present invention to provide a power device having a higher scale of integration than the MOS technology power devices of the related art. In addition, it is an object of the present invention to provide a power device and a method for manufacturing of the power device that is not limited by the processing and alignment tolerances of the MOS technology power device of the related art. In particular, it is an object to provide a power device having a dimension Lp that is a function of a single feature.
According to the present invention, such objects are attained by a MOS technology power device having a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes a body region of a second conductivity type formed in the semiconductor material layer, wherein the body region is an elongated body region. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, and intercalated with a body portion of the body region wherein no dopant of the first conductivity type are provided. In addition, each elementary unit includes insulating material sidewall spacers that insulate edges of the elongated window in the insulated gate layer from a metal layer disposed above the second insulating material layer. The metal layer contacts each body region and source region through the elongated window of each elementary functional unit.
In one embodiment of the MOS-technology power device, the source region includes a plurality of source portions of the first conductivity type that extend in a longitudinal direction of the elongated body region and that are intercalated in the longitudinal direction with body portions of the elongated body region. In an alternative of this embodiment, a length of the source portions is greater than a length of the body portions, and the source portions and the body portions of the elongated body region are substantially aligned in a direction transverse to the longitudinal direction respectively with the source portions and the body portions in body regions of adjacent elementary functional units. In another alternative of this embodiment, a length of the source portions is greater than a length of the body portions, and the source portions and the body portions of the body stripe are substantially shifted in the longitudinal direction with respect to the source portions and the body portions in the adjacent body regions of the adjacent elementary functional units.
In another embodiment of the MOS-technology power device, each source region includes a plurality of source portions extending in the longitudinal direction of the elongated body region and intercalated with the body portions of the body region. A length of the source portions is substantially equal to a length of the body portions, and the source portions and the body portions of the elongated body region are substantially aligned in the transverse direction respectively with the body portions and the source portions of the body regions of the adjacent elementary functional units.
In another embodiment of the MOS-technology power device, the elongated body region includes a first longitudinal half-stripe and a second longitudinal half-stripe that are merged together along a longitudinal edge. Each half-stripe includes a plurality of source portions intercalated in the longitudinal direction with body portions of the half-stripe. The source portions and the body portions of the first longitudinal half-stripe are aligned in the transverse direction, respectively, with the body portions and the source portions in the second longitudinal half-stripe.
In another embodiment of the MOS-technology power device, the elongated body region includes a first longitudinal half-stripe and a second longitudinal half-stripe merged together along a longitudinal edge. The first longitudinal half-stripe includes an elongated source portions extending for substantially an entire length of the first longitudinal half-stripe. The second longitudinal half-stripe includes no dopants of the first conductivity type so that the elongated source region is adjacent the body region for the entire length of the elongated body region.
For each of the embodiments of the present invention, the elongated body region of each elementary functional unit, the layout of the source region inside the elongated body region, which allows the source metal layer to contact the source region and the body region along the length of the elongated body regions, and the sidewall spacers of insulating material that seal the edges of the elongated opening in the insulated gate layer from the source metal layer, result in a reduced dimension Lp of the elongated opening in the insulated gate layer in the direction transverse to the length of the elongated body region. Thus each of the embodiments of the present invention have a reduced dimension Lp of each elementary functional unit, and in an increased density of elementary functional units per unit area.
Also according to the present invention, there is provided a process for manufacturing a MOS technology power device, including forming a first insulating material layer over a semiconductor material layer of a first conductivity type, forming a first conductive material layer over the first insulating material layer, forming a second insulating material layer over the first conductive material layer, and selectively removing the second insulating material layer and the first conductive material layer to open at least one elongated window therein. An elongated body region of a second conductivity type is then formed in the semiconductor material layer under the elongated window, and a source region of the first conductivity type is formed in the elongated body region, in such a way as to be intercalated in the longitudinal dimension with a body portion of the elongated body region wherein no dopants of the first conductivity type are provided. Insulating material sidewall spacers are then formed along edges of the elongated window, and a second conductive material layer is provided over the second insulating material layer, and contacts the source region and the elongated body region through the elongated window.
Preferably, the step of forming the elongated body region includes selectively introducing a dopant of the second conductivity type into the semiconductor material layer using the second insulating material layer as a mask, without the need of a dedicated mask for the formation of a heavily doped deep body region at the center of the elongated body regions of the elementary functional units. In addition, the step of forming the source region preferably involves deposition of photoresist layer over the surface of the chip, selective exposition of the photoresist layer to a light source through a photolithographic mask, and selective removal of the photoresist layer from the surface of the chip. The photoresist layer, the second insulating material layer and the first conductive material layer are used as an implantation mask for introducing dopants of the first conductivity type to form the source regions in the body region. The steps for forming the source region eliminate a need to provide a tolerance for any misalignment between the photolithographic mask used for etching the photoresist layer and a photolithographic mask used for finding the elongated window. With this method, the transverse dimension Lp of the elongated opening in the insulated gate layer, is limited only by an optical resolution limit of the photolithographic apparatus used to open the elongated window in the insulated gate layer.
According to the present invention, the objects of the present invention can also be achieved with a MOS-gated power device such as, for example, a MOSFET, an IGBT, a MOS-gated thyristor (MCT) or other MOS-gated power devices. A MOS-gated power device includes a semiconductor material of a first conductivity type that has a plurality of body regions of a second conductivity type formed in a surface of the semiconductor material. A source region of the first conductivity type is formed in a surface of each of the body regions. An insulated gate layer is disposed above the surface of the semiconductor material layer and includes a plurality of windows in the insulated gate layer that are disposed above each of the plurality of body regions. Each window has one dimension that is limited only by an optical resolution limit of a photolithographic apparatus that defines the window. A plurality of sidewall spacers are disposed at edges of the insulated gate layer in the plurality of windows, and seal the insulated gate layer from a metal layer disposed above the insulated gate layer. The metal layer contacts each of the plurality of body regions and each of the plurality of source regions through the plurality of windows.
Further, according to the present invention a process for manufacturing the MOS-gated power device includes providing a semiconductor substrate including the semiconductor material layer of the first conductivity type disposed over a highly doped semiconductor substrate, and forming the insulated gate layer over the surface of the semiconductor material layer. The insulated gate layer is selectively removed to provide the plurality of windows in the insulated gate layer that expose a surface of the semiconductor material layer beneath each of the plurality of windows. Each of the plurality of window has a transverse dimension that is limited only by the optical resolution limit of the photolithographic apparatus used to selectively remove the insulated gate layer to provide the plurality of windows. The plurality of body regions of the second conductivity type are formed in the surface of the semiconductor material layer through the plurality of windows in the insulated gate layer. The source region of the first conductivity type is also formed in each body region through the plurality of windows in the insulated gate layer. The plurality of sidewall spacers are formed along the edge of the insulated gate layer in each window above the surface of the semiconductor material layer, and the metal layer is provided above the insulated gate layer so as to contact each body region and each source region through each window in the insulated gate layer.
Other objects and features of the present invention will become apparent from the following detailed description when taken in connection with the following drawings. It is to be understood that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention.